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DEST International Workshop on Signal Processing for Sensor Networks
(Will be held as a Pre-Conference  workshop of ISSNIP 2004)

Call for Papers

The International Workshop on Signal Processing for Sensor Networks will be held in conjunction with the International Conference on Intelligent Sensors, Sensor Networks and Information Processing (www.issnip.org) 14-17 December 2004. The primary aim of the workshop is to promote collaborative research between Australian and European researchers, with a view to establishing joint research initiatives, in particular, with the European Commission 6th Framework Program. The workshop is funded by DEST, Australia.

 

The Workshop, focused on the priority area of Information Communications & Technology, will bring together researchers with expertise in pattern recognition, mobile communications, statistical modeling, smart sensors, computational learning and information processing for sensor network related applications. New sensing technologies and sensor networks has been recognized to be one of five technologies that will shape the future of human kind. Significant understanding of biological sensor processing and artificial smart information processing (AI) is available in isolated single sensor systems; however, not much is known about multi-sensor interlinked systems. Recognizing its significance, several billion dollars are currently being invested.

 

To be conducted over two days, the Workshop topics include:

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Statistical Signal Processing

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Independent Component Analysis

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Distributed Information Processing

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Wireless Communications

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Detection and Tracking

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Data Compression and Aggregation

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Pattern Recognition

Invited speakers on each topic will be drawn from both the international experts and local experts in the respective fields. The first two days will be open to the general research community. The third day will be dedicated for the planning and implementation of actions for a future research proposal for funding from the European Commission 6th Framework Program.

Workshop structure and attendance

The workshop is aimed to be a high communicative meeting place for researchers working on similar topics, but from different communities. In order to achieve these goals, the workshop will consist of one or two invited talks, followed by short presentations and longer discussions. Workshop attendance will be limited to registered participants. The selected papers will be published in the conference proceedings.

Submission Procedure

Prospective authors are invited to submit full papers, up to six pages in length, using electronic submission via the conference web site online paper submission system. Papers will be fully refereed and accepted papers will be published in the conference proceedings. Visit Author Guidelines Page for author instructions. For more information contact Dr. Paul Havinga.

 

Please note, you have to select DEST workshop only while submitting your paper using the online submission page. In case you require more time for submitting, please contact Prof. Paul Havinga and obtain the permission from him.

Important Dates

Deadline for Paper Submission: August 15, 2004

Extended Paper Submission Deadline: September 1, 2004

Notification of Acceptance: October 1, 2004

Camera-ready Paper: October 15, 2004

Program Committee

M. Palaniswami, Dept. of Electrical and Electronic Engineering, The University of Melbourne, Australia

swami (at) ee.mu.oz.au

E. Oja, Dept. of Computer Science and Engineering, Helsinki University of Technology, Finland

  (at)  

P. Havinga, Dept. of EEMCS/Embedded Systems, University of Twente, The Netherlands

P.J.M.Havinga  (at) ewi.utwente.nl

A. Zoubir (expatriate), Institute of Telecommunications, Darmstadt University of Technology, Germany

  (at)  

D. Ralph (expatriate), Dept. of Engineering, Cambridge University, UK

  (at)  

S. Low (expatriate), Dept. of Computer Science and Electrical Engineering, Caltech, USA

  (at)  

P. Bartlett (expatriate), Division of Computer Science and Dept. of Statistics, UC Berkeley, USA

  (at)  

U. Ramacher, Infineon, Germany

  (at)  

J. Harnisch, Infineon, Germany

  (at)